Method and apparatus to enable DRAM to support low-latency...

Details Method and apparatus to enable DRAM to support low-latency... Method and apparatus to enable DRAM to support low-latency...

2008-01-29

2008-01-29

Portka, Gary (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000

Reexamination Certificate

active

07325099

ABSTRACT:
Method and apparatus to enable slower memory, such as dynamic random access memory (DRAM)-based memory, to support low-latency access using vertical caching. Related function metadata used for packet-processing functions, including metering and flow statistics, is stored in an external DRAM-based store. In one embodiment, the DRAM comprises double data-rate (DDR) DRAM. A network processor architecture is disclosed including a DDR assist with data cache coupled to a DRAM controller. The architecture further includes multiple compute engines used to execute various packet-processing functions. One such function is a DDR assist function that is used to pre-fetch a set of function metadata for a current packet and store the function metadata in the data cache. Subsequently, one or more packet-processing functions may operate on the function metadata by accessing it from the cache. After the functions are completed, the function metadata are written back to the DRAM-based store. The scheme provides similar performance to SRAM-based schemes, but uses much cheaper DRAM-type memory.

REFERENCES:
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patent: 2003/0152076 (2003-08-01), Lee et al.
patent: 2003/0191866 (2003-10-01), Wolrich et al.
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patent: 2005/0289551 (2005-12-01), Wojtkiewicz et al.
patent: 2006/0010339 (2006-01-01), Klein

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