Using redundant routing to reduce susceptibility to single...

Details Using redundant routing to reduce susceptibility to single... Using redundant routing to reduce susceptibility to single...

Filed on

2008-06-10

Date issued

2008-06-10

Examiner

Chiang, Jack (Department: 2825)

Patent Class

Computer-aided design and analysis of circuits and semiconductor

SubClass

Nanotechnology related integrated circuit design

Other Related Categories

C716S030000, C326S009000, C326S014000

Type

Reexamination Certificate

Status

active

Patent number

07386826

Description

ABSTRACT:
Methods of implementing designs in programmable logic devices (PLDs) to reduce susceptibility to single-event upsets (SEUs) by taking advantage of the fact that most PLD designs leave many routing resources unused. The unused routing resources can be used to provide duplicate routing paths between source and destination of signals in the design. The duplicate paths are selected such that an SEU in a routing multiplexer included in each path simply switches the signal between the two paths. Thus, if one path is disabled due to an SEU, the other path can still provide the necessary connection, and the functionality of the design is unaffected. The methods can be applied, for example, to routing software for field programmable gate arrays (FPGAs) having programmable routing multiplexers controlled by static RAM-based configuration memory cells.

REFERENCES:
patent: 5552721 (1996-09-01), Gould
patent: 5552722 (1996-09-01), Kean
patent: 5581198 (1996-12-01), Trimberger
patent: 5598108 (1997-01-01), Pedersen
patent: 5631578 (1997-05-01), Clinton et al.
patent: 5867507 (1999-02-01), Beebe et al.
patent: 5925920 (1999-07-01), MacArthur et al.
patent: 6049487 (2000-04-01), Plants et al.
patent: 6127864 (2000-10-01), Mavis et al.
patent: 6211695 (2001-04-01), Agrawal et al.
patent: 6505337 (2003-01-01), Wittig et al.
patent: 6617912 (2003-09-01), Bauer
patent: 6621296 (2003-09-01), Carberry et al.
patent: 6621298 (2003-09-01), Agrawal et al.
patent: 6671202 (2003-12-01), Bauer
patent: 6798270 (2004-09-01), Bauer
patent: 6810513 (2004-10-01), Vest
patent: 6838899 (2005-01-01), Plants
patent: 6903571 (2005-06-01), Trimberger
patent: 7023235 (2006-04-01), Hoff
patent: 7111215 (2006-09-01), Keller et al.
patent: 7200822 (2007-04-01), McElvain
patent: 2001/0037482 (2001-11-01), Plants
patent: 2002/0095649 (2002-07-01), Sample et al.
patent: 2003/0173993 (2003-09-01), Gupta
patent: 2004/0080999 (2004-04-01), Madurawe
de Lima; “Designing single event upset mitigation techniques for large SRAM-based FPGA devices”; Thesis Proposal; Porto Alegre, Feb. 11, 2002 [online], [tetieved on Apr. 27, 2007]. Retreived from the Internet <URL:http://www.inf.ufrgs.br/˜fglima/lima—proposal.pdf>.
Phil Brinkley, Carl Carmichael; XAPP181 (v1.0); “SEU Mitigation Design Techniques for the XQR4000XL”; Mar. 15, 2000; available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124 or http//www.xilinx.com.; pp. 1-14.
U.S. Appl. No. 09/783,821, filed Feb. 14, 2001, Carmichael et al.

Affiliated with

Also associated with

Rating

Using redundant routing to reduce susceptibility to single... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Using redundant routing to reduce susceptibility to single..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Using redundant routing to reduce susceptibility to single... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2800470