Method of displaying a guard ring within an integrated circuit

Details Method of displaying a guard ring within an integrated circuit Method of displaying a guard ring within an integrated circuit

2008-03-25

2008-03-25

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07350160

ABSTRACT:
The invention displays a guard ring within an integrated circuit design by determining positions of the logic devices within the integrated circuit design, incorporating the guard ring into the integrated circuit design, and displaying the logic devices and the guard ring either graphically, semantically, or symbolically in a single display. The symbolic display comprises a parameterized symbol. The parameterized symbol displays parameters including the type of circuit, the type of guard ring and the efficiency of the guard ring. The invention displays the logic devices and the guard ring graphically by illustrating relative positions of the logic devices and the guard ring.

REFERENCES:
patent: 4937756 (1990-06-01), Hsu et al.
patent: 4988636 (1991-01-01), Masleid et al.
patent: 5051917 (1991-09-01), Gould et al.
patent: 5369595 (1994-11-01), Gould et al.
patent: 5402358 (1995-03-01), Smith et al.
patent: 6073343 (2000-06-01), Petrick et al.
patent: 6078085 (2000-06-01), Suzuki
patent: 6086627 (2000-07-01), Bass et al.
patent: 6157066 (2000-12-01), Kobayashi
patent: 6321367 (2001-11-01), Chun et al.
patent: 6424022 (2002-07-01), Wu et al.
patent: 6446250 (2002-09-01), Becker
patent: 6449748 (2002-09-01), Jeng et al.
patent: 6480995 (2002-11-01), Schmidt et al.
patent: 6509617 (2003-01-01), Hiraga
patent: 6509622 (2003-01-01), Ma et al.
patent: 6550047 (2003-04-01), Becker
patent: 6734567 (2004-05-01), Chiu et al.
patent: 6900969 (2005-05-01), Salling et al.
patent: 2001/0053948 (2001-12-01), Kishida et al.
patent: 2004/0114287 (2004-06-01), Salling et al.
patent: 2004/0164937 (2004-08-01), Liedenbaum et al.
Quincke J., Novel test structure for the investigation of the efficiency of guard ring used for I/O latch-up prevention, Mar. 1990, vol. 3, pp. 35-39.
Ker et al., Automatic methodology for placing the guard ring into chip layout to prevent latch-up in CMOS IC's, Sep. 2001, vol. 1, pp. 113-116.

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