Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2008-07-22
2008-07-22
Warren, Matthew E (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S327000, C257S347000, C257S619000, C257SE29295
Reexamination Certificate
active
07402856
ABSTRACT:
A non-planar microelectronic device, a method of fabricating the device, and a system including the device. The non-planar microelectronic device comprises: a substrate body including a substrate base and a fin, the fin defining a device portion at a top region thereof; a gate dielectric layer extending at a predetermined height on two laterally opposing sidewalls of the fin, the predetermined height corresponding to a height of the device portion; a device isolation layer on the substrate body and having a thickness up to a lower limit of the device portion; a gate electrode on the device isolation layer and further extending on the gate dielectric layer; an isolation element extending on the two laterally opposing sidewalls of the fin up to a lower limit of the gate dielectric layer, the isolation element being adapted to reduce any fringe capacitance between the gate electrode and regions of the fin extending below the device portion.
REFERENCES:
patent: 5804848 (1998-09-01), Mukai
patent: 5844278 (1998-12-01), Mizuno et al.
patent: 5899710 (1999-05-01), Mukai
patent: 6018176 (2000-01-01), Lim
patent: 6066869 (2000-05-01), Noble et al.
patent: 6413802 (2002-07-01), Hu et al.
patent: 6459123 (2002-10-01), Enders et al.
patent: 6472258 (2002-10-01), Adkisson et al.
patent: 6525403 (2003-02-01), Inaba et al.
patent: 6562665 (2003-05-01), Yu
patent: 6583469 (2003-06-01), Fried et al.
patent: 6611029 (2003-08-01), Ahmed et al.
patent: 6630388 (2003-10-01), Sekigawa et al.
patent: 6642090 (2003-11-01), Fried et al.
patent: 6657259 (2003-12-01), Fried et al.
patent: 6689650 (2004-02-01), Gambino et al.
patent: 6770516 (2004-08-01), Wu et al.
patent: 6787402 (2004-09-01), Yu
patent: 6794718 (2004-09-01), Nowak et al.
patent: 6798000 (2004-09-01), Luyken et al.
patent: 6800910 (2004-10-01), Lin et al.
patent: 6803631 (2004-10-01), Dakshina-Murthy et al.
patent: 6812075 (2004-11-01), Fried et al.
patent: 6815277 (2004-11-01), Fried et al.
patent: 6821834 (2004-11-01), Ando
patent: 6833588 (2004-12-01), Yu et al.
patent: 6835614 (2004-12-01), Hanafi et al.
patent: 6635909 (2005-02-01), Clark et al.
patent: 6849884 (2005-02-01), Clark et al.
patent: 6869868 (2005-03-01), Chiu et al.
patent: 6885055 (2005-04-01), Lee
patent: 6897527 (2005-05-01), Dakshina-Murthy et al.
patent: 7224019 (2007-05-01), Hieda et al.
patent: 2005/0173768 (2005-08-01), Lee et al.
patent: 2006/0270156 (2006-11-01), Kim et al.
Yang-Kyu Choi, et al., Sub-20nm CMOS FinFet Technologies, IEEE, 2001, pp. 19.1.1-19.1.4, IEDM 01, Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, USA.
Jong-Tae Park, et al., Pi-Gate Soi Mosfet, IEEE Electron Device Letters, Aug. 2001, 405-406, vol. 22, University of California, Berkeley, USA.
Brask Justin K.
Chau Robert S.
Doyle Brian S.
Kavalieros Jack T.
Intel Corporation
Lane Scott M.
Warren Matthew E
LandOfFree
Non-planar microelectronic device having isolation element... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Non-planar microelectronic device having isolation element..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-planar microelectronic device having isolation element... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2783872