Multi-priority encoder

Details Multi-priority encoder Multi-priority encoder

2011-08-02

2011-08-02

Bragdon, Reginald G (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711SE12097, C341S160000

Reexamination Certificate

active

07991947

ABSTRACT:
A multi-priority encoder includes a plurality of interconnected, single-priority encoders arranged in descending priority order. The multi-priority encoder includes circuitry for blocking a match output by a lower level single-priority encoder if a higher level single-priority encoder outputs a match output. Match data is received from a content addressable memory, and the priority encoder includes address encoding circuitry for outputting the address locations of each highest priority match line flagged by the highest priority indicator. Each single-priority encoder includes a highest priority indicator which has a plurality of indicator segments, each indicator segment being associated with a match line input.

REFERENCES:
patent: 3634829 (1972-01-01), Campi et al.
patent: 6307767 (2001-10-01), Fuh
patent: 6462694 (2002-10-01), Miyatake
patent: 6693814 (2004-02-01), McKenzie et al.

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