Methods and apparatus for providing multi-processor access to sh

Details Methods and apparatus for providing multi-processor access to sh Methods and apparatus for providing multi-processor access to sh

1998-05-22

2000-12-19

Ray, Gopal C.

Electrical computers and digital data processing systems: input/

Access arbitrating

711100, 711147, 710107, 710113, G06F 1316, G06F 1200, G06F 1336

Patent

active

061638285

ABSTRACT:
A multi-processor interface is described having two processors. The first processor lacks a ready input and is continuously operating. The two processors share a memory, where the operation of the second processor is suspended when it requests memory access while the first processor has memory access. The multi-processor interface also includes a bus arbiter which selectively connects the memory to the first or second processor. The bus arbiter suspends operation of the second processor when the second processor requests memory access while the first processor has memory access.

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By Alan Clements, "Microcomputer Design and Construction" Prentice Hall International, pp. 378-385.

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