Memory cells and select gates of NAND memory arrays

Details Memory cells and select gates of NAND memory arrays Memory cells and select gates of NAND memory arrays

2008-07-22

2008-07-22

Vu, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S257000

Reexamination Certificate

active

07402861

ABSTRACT:
A select gate of a NAND memory array has a first dielectric layer formed on a semiconductor substrate. A first conductive layer is formed on the first dielectric layer. Conductive spacers are formed on sidewalls of the first conductive layer and are located between an upper surface of the first conductive layer and the first dielectric layer. A second dielectric layer overlies the first conductive layer and the conductive spacers. A second conductive layer is formed on the second dielectric layer. A third conducive layer is formed on the second conductive layer, passes though a portion of the second conductive layer and the second dielectric layer, and contacts the first conductive layer. The third conductive layer electrically connects the first and second conductive layers.

REFERENCES:
patent: 5618742 (1997-04-01), Shone
patent: 5650345 (1997-07-01), Ogura
patent: 6562681 (2003-05-01), Tuan et al.
patent: 6642570 (2003-11-01), Tseng
patent: 2001/0009289 (2001-07-01), Jeong
patent: 2004/0178456 (2004-09-01), Park et al.

Affiliated with

Also associated with

Rating

Memory cells and select gates of NAND memory arrays does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory cells and select gates of NAND memory arrays, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory cells and select gates of NAND memory arrays will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2777234