Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2011-08-16
2011-08-16
Booth, Richard A. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S653000
Reexamination Certificate
active
07998859
ABSTRACT:
A method is disclosed for metallizing a substrate comprising an interconnect feature in the manufacture of a microelectronic device, wherein the interconnect feature comprises a bottom, a sidewall, and a top opening having a diameter, D. The method comprises the following steps: depositing a barrier layer on the bottom and the sidewall of the interconnect feature, the barrier layer comprising a metal selected from the group consisting of ruthenium, tungsten, tantalum, titanium, iridium, rhodium, and combinations thereof; contacting the substrate comprising the interconnect feature comprising the bottom and sidewall having the barrier layer thereon with an aqueous composition comprising a reducing agent and a surfactant; and depositing copper metal onto the bottom and the sidewall of the interconnect feature having the barrier layer thereon.
REFERENCES:
patent: 4220678 (1980-09-01), Feldstein
patent: 4258087 (1981-03-01), Feldstein
patent: 4282271 (1981-08-01), Feldstein
patent: 4301190 (1981-11-01), Feldstein
patent: 4317846 (1982-03-01), Feldstein
patent: 4318940 (1982-03-01), Feldstein
patent: 4339476 (1982-07-01), Feldstein
patent: 4642161 (1987-02-01), Akahoshi et al.
patent: 5721014 (1998-02-01), Fakler et al.
patent: 5753309 (1998-05-01), Fakler et al.
patent: 5900186 (1999-05-01), Fakler et al.
patent: 6086956 (2000-07-01), Fakler et al.
patent: 6322656 (2001-11-01), Fakler et al.
patent: 6794288 (2004-09-01), Kolics et al.
patent: 2004/0084773 (2004-05-01), Johnston et al.
patent: 2006/0240187 (2006-10-01), Weidman
patent: 2006/0246699 (2006-11-01), Weidman et al.
patent: 2006/0252252 (2006-11-01), Zhu et al.
patent: 2006/0264043 (2006-11-01), Stewart et al.
patent: 2007/0004201 (2007-01-01), Lubomirsky et al.
patent: 2007/0099422 (2007-05-01), Wijekoon et al.
Electroless Copper Deposition on Ruthenium for Damascene Interconnects; ECS Transactions; Q. Chen, X. Lin, C. Valverde, V. Paneccasio, R. Hurtubise, P. Ye, E. Kudrak, and J. Abys; Sep. 27, 2007.
211th ECS Abstract of Electroless Copper Deposition on Ruthenium for Damascene Interconnects; ECS Transactions; Q. Chen and X. Lin; et al.; Jan. 26, 2007.
PowerPoint Presentation: Electroless Copper Deposition on Ru for Damascene Interconnect Applications; Q. Chen, X. Lin, C. Valverde, V. Paneccasio, R. Hurtubise, P. Ye, E Kudrak, and J. Abys; ECS Meeting; May 9, 2007.
Abys Joseph A.
Chen Qingyun
Hurtubise Richard
Lin Xuan
Paneccasio, Jr. Vincent
Booth Richard A.
Enthone Inc.
Senniger Powers LLP
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