Soft error resistant memory cell and method of manufacture

Details Soft error resistant memory cell and method of manufacture Soft error resistant memory cell and method of manufacture

2008-04-08

2008-04-08

Lam, David (Department: 2827)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S149000, C365S205000, C257S903000, C438S239000

Reexamination Certificate

active

07355880

ABSTRACT:
A semiconductor device memory cell (100) can include a built-in capacitor for reducing a soft-error rate (SER). A memory cell (100) can include a first inverter (102) and second inverter (104) arranged in a cross-coupled configuration. A capacitor (110) can be coupled between a first storage node (106) and second storage node (108). A capacitor (110) can be a “built-in” capacitor formed with interconnect wirings utilized to connect memory cell circuit components.

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patent: 6104053 (2000-08-01), Nagai
patent: 6504788 (2003-01-01), Nil et al.
patent: 6693820 (2004-02-01), Nil et al.
patent: 6696873 (2004-02-01), Hazucha et al.
patent: 6750113 (2004-06-01), Armacost et al.

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