CPU system, bus bridge, control method therefor, and...

Details CPU system, bus bridge, control method therefor, and... CPU system, bus bridge, control method therefor, and...

2008-01-01

2008-01-01

Rinehart, Mark H. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S119000, C710S200000

Reexamination Certificate

active

07315913

ABSTRACT:
In a system having an arrangement that a CPU (101) connected to a bus (107) via bus bridge (103) and a CPU102connected to a bus (107) via bus bridge (104), when the bus bridge (103) receives a semaphore acquisition request from the CPU (101), it controls acquisition of a semaphore on the basis of a semi_out signal received from the bus bridge (104) and a priority order received via a signal line (112).

REFERENCES:
patent: 4257095 (1981-03-01), Nadir
patent: 6240526 (2001-05-01), Petivan et al.
patent: 6549961 (2003-04-01), Kloth
patent: 05-020279 (1993-01-01), None

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