Distribution and synchronization of a divided clock signal

Details Distribution and synchronization of a divided clock signal Distribution and synchronization of a divided clock signal

2011-03-01

2011-03-01

Barnie, Rexford N (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Reexamination Certificate

active

07898296

ABSTRACT:
Methods and circuitry for distributing and synchronizing a divided clock signal in an electronic device are disclosed. In one aspect of an embodiment, a series of registers distributes the divided clock signal and the series of registers is clocked by a full-speed clock signal from which the divided clock signal is derived. In another aspect, the divided clock signal and the full-speed clock signal are distributed to IO circuitry of the electronic device. In yet another aspect, the divided clock signal is also distributed to circuitry in a core of the electronic device.

REFERENCES:
patent: 5557649 (1996-09-01), Scheckel et al.
patent: 6566918 (2003-05-01), Nguyen
patent: 6993671 (2006-01-01), Pricer et al.
patent: 6996736 (2006-02-01), Nguyen et al.
patent: 7228451 (2007-06-01), Nguyen et al.

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