Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2011-08-02
2011-08-02
Cao, Phat X (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S471000, C438S476000, C438S400000, C438S404000, C438S423000, C438S478000, C438S479000, C438S481000, C438S489000, C257S594000, C257S616000, C257S617000
Reexamination Certificate
active
07989306
ABSTRACT:
Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions.
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Office Action dated Apr. 5, 2011, in U.S. Appl. No. 11/867,995.
Liu Xuefeng
Rassel Robert M.
Voldman Steven H.
Canale Anthony
Cao Phat X
Garrity Diana C
International Business Machines - Corporation
Roberts Mlotkowski Safran & Cole P.C.
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