Semiconductor integrated circuit device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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Reexamination Certificate

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08006145

ABSTRACT:
A semiconductor integrated circuit device related to an embodiment of the present invention includes an address register which includes an internal selection circuit connected with a control circuit, a signal generation instruction circuit which instructs the control circuit so that a predetermined internal control signal is generated, a latch circuit, a plurality of which are arranged corresponding to a number of bits of test parameter data, the latch circuit latching test result data which is provided from the data program/read circuit and outputting the test result data to the selection circuit and externally, the control circuit generating an internal control signal which activates the selection circuit at a timing at which a fixed value data of the test parameter data is changed, and the selection circuit controlling a test so that a fixed value data of the test parameter data is changed.

REFERENCES:
patent: 6285597 (2001-09-01), Kawahara et al.
patent: 6496418 (2002-12-01), Kawahara et al.
patent: 7146549 (2006-12-01), Kanba
patent: 2004/0042331 (2004-03-01), Ikehashi et al.
patent: 2003-344500 (2003-12-01), None
U.S. Appl. No. 12/252,724, filed Oct. 16, 2008, Kazushige Kanda.

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