Semiconductor memory having multiple redundant columns with offs

Details Semiconductor memory having multiple redundant columns with offs Semiconductor memory having multiple redundant columns with offs

1999-07-16

2000-12-19

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Bad bit

365210, G11C 1300

Patent

active

061634891

ABSTRACT:
A memory device with a segmented column architecture that allows for single bank repair across any two row blocks is disclosed. Multiple redundant columns are provided that have offset segment boundaries, i.e., a first redundant column is divided into four segments consisting of row block <0,1>, row block <2,3>, row block <4,5> and row block <6,7>, and a second redundant column is divided into four segments consisting of row block <1,2>, row block <3,4>, row block <5,6> and row block <0,7>. By offsetting the segment boundaries, the repair of the memory device can be optimized by repairing any two adjacent row blocks with only one column segment by selecting the appropriate redundant column segment.

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patent: 5608678 (1997-03-01), Lysinger
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