Refresh signal generating circuit

Details Refresh signal generating circuit Refresh signal generating circuit

2011-03-08

2011-03-08

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S233100, C365S236000

Reexamination Certificate

active

07903491

ABSTRACT:
A refresh signal generating circuit of a semiconductor memory device includes a flag signal generator which generates a flag signal in response to a refresh signal and a precharge signal, a clock enable signal buffer which generates first and second buffer enable signals based on an external clock enable signal in response to the flag signal, and a chip select signal buffer which generates an internal chip select signal based on an external chip select signal in response to the flag signal.

REFERENCES:
patent: 6665225 (2003-12-01), Tsujino
patent: 7359269 (2008-04-01), You
patent: 2003/0185078 (2003-10-01), Tsukude
patent: 10-2001-0004670 (2001-01-01), None
patent: 10-2001-0057488 (2001-07-01), None
patent: 10-2004-0100249 (2004-12-01), None
patent: 10-2004-0102727 (2004-12-01), None

Affiliated with

Also associated with

Rating

Refresh signal generating circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Refresh signal generating circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Refresh signal generating circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2755912