Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2008-01-29
2008-01-29
Nguyen, Cuong (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S350000, C257S351000
Reexamination Certificate
active
07323748
ABSTRACT:
A semiconductor device includes a substrate having first and second regions, a first insulating film formed on the substrate in the first region, a first epitaxial layer formed on the substrate in the second region and having an upper surface higher than an upper surface of the first insulating film, and a first semiconductor layer formed on the first insulating film with a space provided with respect to the first epitaxial layer, having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer and having a tapered surface faced to a side surface of the first epitaxial layer.
REFERENCES:
patent: 6214653 (2001-04-01), Chen et al.
patent: 6214694 (2001-04-01), Leobandung et al.
patent: 6429488 (2002-08-01), Leobandung et al.
patent: 6531754 (2003-03-01), Nagano et al.
patent: 6630714 (2003-10-01), Sato et al.
patent: 6750486 (2004-06-01), Sugawara et al.
patent: 6835981 (2004-12-01), Yamada et al.
patent: 6855976 (2005-02-01), Nagano et al.
patent: 6906384 (2005-06-01), Yamada et al.
patent: 7148543 (2006-12-01), Yamada et al.
patent: 2003/0057490 (2003-03-01), Nagano et al.
patent: 2004/0150044 (2004-08-01), Nagano et al.
patent: 2004/0183131 (2004-09-01), Nagano et al.
patent: 2006/0084249 (2006-04-01), Yamada
patent: 7-106434 (1995-04-01), None
patent: 8-17694 (1996-01-01), None
patent: 8-316431 (1996-11-01), None
patent: 10-303385 (1998-11-01), None
patent: 11-17001 (1999-01-01), None
patent: 11-238860 (1999-08-01), None
patent: 2000-91534 (2000-03-01), None
patent: 2000-243944 (2000-09-01), None
Robert Hannon, et al., “0.25 μm Merged Bulk DRAM and SOI Logic using Patterned SOI”, Symposium on VLSI Technology Digest of Technical Papers, 2000, pp. 66-67.
H.L. Ho, et al., “A 0.13 μM High-Performance SOI Logic Technology with Embedded DRAM for System-On-A-Chip Application”, IEDM Tech. Dig., 2001, pp. 503-506.
T. Yamada, et al., “An Embedded DRAM Technology on SOI/BULK Hydrid Substrate Formed with SEG Progress for High-End SOC Application”, Symposium on VLSI Technology Digest of Technical Papers, 2002, pp. 112-113.
Hajime Nagano, et al., “SOI/Bulk Hybrid Wafer Process Using SEG (Selective Epitaxial Growth) Technique for High-End SoC Applications”, Extended Abstracts of the 2002 International Conference on Solid State Devices and Material, 2002, pp. 442-443.
Takashi Yamada, et al., “An Embedded DRAM Technology in SOI for High-End SoC Application”, Semi Technology Symposium, 2002, pp. 2-39-2-44 (with English Abstract).
Hamamoto Takeshi
Nagano Hajime
Yamada Takashi
Kabushiki Kaisha Toshiba
Nguyen Cuong
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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