Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-04-29
2008-04-29
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07367002
ABSTRACT:
A method, system and computer program product for performing parametric reduction of sequential designs. According to an embodiment of the present invention, the method includes receiving an initial design including one or more primary inputs, one or more targets, and one or more state elements. A cut of the initial design including one or more cut gates is identified, and a relation of one or more values producible to the one or more cut gates in terms of the one or more primary inputs and the one or more state elements is computed. The relation is synthesized to form a gate set, and an abstracted design is formed from the gate set. Verification is performed on the abstracted design to generate verification results.
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Baumgartner Jason Raymond
Janssen Geert
Mony Hari
Paruthi Viresh
Chiang Jack
Dillon & Yudell LLP
Doan Nghia M.
International Business Machines - Corporation
Salys Casimer K.
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