Wire structure, a thin film transistor substrate of using...

Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Including integrally formed optical element

Reexamination Certificate

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Details

C438S149000, C438S151000, C438S128000, C257S072000, C257S059000, C257S347000

Reexamination Certificate

active

07396695

ABSTRACT:
A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on the gate insulating layer and the semiconductor pattern. A protective layer is formed on the data wire. Pixel electrodes connected to the drain electrode via contact holes are formed on the protective layer. The gate wire and the data wire include triple layers of an adhesion layer, a Ag containing layer and a protection layer. The adhesion layer includes one of Cr, Cr alloy, Ti, Ti alloy, Mo, Mo alloy, Ta and Ta alloy, the Ag containing layer includes Ag or Ag alloy, and the protection layer includes one of IZO, Mo, Mo alloy, Cr and Cr alloy.

REFERENCES:
patent: 6323051 (2001-11-01), Shimada
patent: 6468822 (2002-10-01), Maeda et al.
patent: 10062815 (1998-03-01), None
patent: 10062816 (1998-03-01), None
patent: 2001005038 (2001-01-01), None
patent: 2001223365 (2001-08-01), None
patent: 1020000068418 (2000-11-01), None
patent: 1020010010117 (2001-02-01), None

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