Semiconductor memory having charge trapping memory cells and...

Details Semiconductor memory having charge trapping memory cells and... Semiconductor memory having charge trapping memory cells and...

2008-04-29

2008-04-29

Andujar, Leonardo (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S535000, C438S300000

Reexamination Certificate

active

07365382

ABSTRACT:
A semiconductor memory having charge trapping memory cells, where the direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.

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patent: 2004/0026745 (2004-02-01), Itoh et al.
patent: 2004/0262665 (2004-12-01), Iwata et al.
patent: 10039441 (2002-02-01), None
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patent: 10204873 (2003-10-01), None
patent: WO 2004/053982 (2004-06-01), None

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