Method and apparatus for implementing adjustable logic threshold

Details Method and apparatus for implementing adjustable logic threshold Method and apparatus for implementing adjustable logic threshold

1999-05-05

2000-12-19

Nelms, David

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326121, 326 97, H03K 1996

Patent

active

061631736

ABSTRACT:
Methods and apparatus are provided for implementing adjustable logic threshold in dynamic circuits. The dynamic circuit includes an intermediate precharge node. An output logic stage is connected to the intermediate precharge node. A threshold adjustment circuit is connected to the output logic stage. The threshold adjustment circuit receives a selection input to adjust a threshold of the output logic stage. The threshold adjustment circuit is formed of a first transistor and a second transistor coupled in parallel with a pair of series connected transistors included in the output logic stage. One or both of the first transistor and second transistor are selectively activated to adjust the threshold of the output logic stage.

REFERENCES:
patent: 5399918 (1995-03-01), Taylor et al.
patent: 5483181 (1996-01-01), D'Souza
patent: 5965925 (1999-10-01), Kornachuk et al.

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