Semiconductor memory device and method for manufacturing same

Details Semiconductor memory device and method for manufacturing same Semiconductor memory device and method for manufacturing same

2011-08-02

2011-08-02

Le, Vu A (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S049110, C365S189090, C365S210120

Reexamination Certificate

active

07990756

ABSTRACT:
Disclosed herein is a semiconductor memory device including a plurality of memory cells including first and second inverters each having first and second driver transistors and first and second load transistors and including first and second memory node, and first and second transfer transistors. The of the first and second transfer transistors is connected to each of the first and memory nodes respectively. The memory cell is connected to a bit line and complementary bit line via the first and second transfer transistors respectively wherein a supply voltage applied to the bit line and the complementary bit line is lower than a supply voltage applied to the load transistors, and at least a memory-node-side end of a gate insulating film of the first driver transistor, second driver transistor, first load transistor, and the second load transistor have a thickness larger than a thickness of a gate insulating film of the other part.

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J. Pille et al.; Implementation of the Cell Broadband Engine in a 65nm S0I Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V; IEEE International Solid-State Circuits Conference; 2007.
Japanese Office Action issued on Sep. 29, 2009 in connection with JP Application No. 2007-249791.
Japanese Office Action issued on Nov. 2, 2010 in connection with counterpart JP Application No. 2007-249791.

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