Electrical computers and digital processing systems: support – Digital data processing system initialization or configuration
Reissue Patent
2011-06-07
2011-06-07
Suryawanshi, Suresh K (Department: 2115)
Electrical computers and digital processing systems: support
Digital data processing system initialization or configuration
C713S100000, C710S008000
Reissue Patent
active
RE042444
ABSTRACT:
A reconfigurable computer system based on programmable logic is provided. A system design language may be used to write applications. The applications may be automatically partitioned into software components and programmable logic resource components. A virtual computer operating system may be provided to schedule and allocate system resources. The virtual computer operating system may include a virtual logic manager that may increase the capabilities of programmable logic resources in the system.
REFERENCES:
patent: 5068823 (1991-11-01), Robinson
patent: 5128871 (1992-07-01), Schmitz
patent: 5134884 (1992-08-01), Anderson
patent: 5142625 (1992-08-01), Nakai
patent: 5442792 (1995-08-01), Chun
patent: 5469003 (1995-11-01), Kean
patent: 5535342 (1996-07-01), Taylor
patent: 5535406 (1996-07-01), Kolchinsky
patent: 5541849 (1996-07-01), Rostoker et al.
patent: 5548228 (1996-08-01), Madurawe
patent: 5579530 (1996-11-01), Solomon et al.
patent: 5684980 (1997-11-01), Casselman
patent: 5705938 (1998-01-01), Kean
patent: 5761484 (1998-06-01), Agarwal et al.
patent: 5819064 (1998-10-01), Razdan et al.
patent: 5822570 (1998-10-01), Lacey
patent: 5835734 (1998-11-01), Alkalaj et al.
patent: 5859878 (1999-01-01), Phillips et al.
patent: 5946219 (1999-08-01), Mason et al.
patent: 5966534 (1999-10-01), Cooke et al.
patent: 5968161 (1999-10-01), Southgate
patent: 5999990 (1999-12-01), Sharrit et al.
patent: 6011740 (2000-01-01), Trimberger
patent: 6044211 (2000-03-01), Jain
patent: 6068823 (2000-05-01), Sanchez et al.
patent: 6085317 (2000-07-01), Smith
patent: 6219149 (2001-04-01), Kawata et al.
patent: 6219628 (2001-04-01), Kodosky et al.
patent: 6219785 (2001-04-01), Smith
patent: 6226776 (2001-05-01), Panchul et al.
patent: 6282627 (2001-08-01), Wong et al.
patent: 6457173 (2002-09-01), Gupta et al.
patent: 6477683 (2002-11-01), Killian et al.
patent: 6510546 (2003-01-01), Blodget
patent: 6608638 (2003-08-01), Kodosky et al.
patent: 6625797 (2003-09-01), Edwards et al.
patent: 6658564 (2003-12-01), Smith et al.
patent: 6745160 (2004-06-01), Gupta et al.
patent: 2002/0100032 (2002-07-01), Metzgen
patent: 2002/0124238 (2002-09-01), Metzgen
patent: 0 419 105 (1991-03-01), None
patent: 0 419 105 (1991-03-01), None
patent: 419105 (1991-03-01), None
patent: 0 445 913 (1991-09-01), None
patent: 0 445 913 (1991-09-01), None
patent: 0 759 662 (1997-02-01), None
patent: 0 759 662 (1997-02-01), None
patent: 0 801 351 (1997-10-01), None
patent: 0 801351 (1997-10-01), None
patent: 801351 (1997-10-01), None
patent: 0 829 812 (1998-03-01), None
patent: 0 829 812 (1998-03-01), None
patent: 1 444 084 (1976-07-01), None
patent: 03-214370 (1991-09-01), None
patent: 08-305547 (1996-11-01), None
patent: 09-218781 (1997-08-01), None
patent: 10-171645 (1998-06-01), None
patent: WO 94/10627 (1994-05-01), None
patent: WO 97/09930 (1997-03-01), None
patent: WO 97/13209 (1997-04-01), None
patent: WO 98/031102 (1998-07-01), None
patent: WO 00/31652 (2000-06-01), None
patent: WO 00/38087 (2000-06-01), None
patent: WO 00/63719 (2000-10-01), None
Stroy et al. “Inter-Domain Movement of Functionality as a Repartitioning Strategy for Hardward/Software Co-Design” Journal of Systems Architecture, Elsevier Science Publishers BV., Amsterdam, NL, vol. 43, No. 1/05, pgs. 87-98 Mar. 1, 1997 X000679758.
Edwards et al. “Acceleration of Software Algorithms Using Hardware/Software Co-Design Techniques” Journal of Systems Architecture, Elsevier Science Publishers BV., Amsterdam, NL>, vol. 42, No. 9/10, pgs. 697-707, XP000643485.
Edwards et al. “Hardware/software partitioning for performance enhancement” pgs. 2-5, Jan. 1, 1995, XP006529055.
Ernst et al. “The Cosyma Environment for Hardware/Software Cosynthesis of Small Embedded Systems” Microprocessors and Microsystems, IPC Business Press Ltd. London, GB vol. 20, No. 3 May 1, 1996 pp. 159-166, XP000590927.
Parkinson et al. “Profiling in the ASP Codesign environment” Systems Synthesis, 1995, Proceedings of the Eighth International Symposium on Cannes, France Sep. 13-15, 1995, Los Alamitos, CA, USA, IEEE pp. 128-133, XP010192178.
M Wazlowski et al., “Prism-II Complier and Architecture,” IEEE, 1993, pp. 9-16.
David Wo et al., “Compiling to the gate Level for a Reconfigurable Co-Processor,” IEEE, 1994, pp. 147-154.
Christian Iseli et al., “A C++ compiler for FPFA custom execution units synthesis,” IEEE, 1995, pp. 173-179.
Ian Page, “Constructing Hardware-Software Systems from a Single Description,” Journal of VLSI Signal Processing, vol. 12, No. 1, Jan. 1996, pp. 87-107.
M.D. Edwards, J. Forrest—“Software acceleration using programmable hardware devices,” Jan. 1996, p. 55-63.
Tsuyoshi Isshiki et al., “Bit-Serial Pipeline Synthesis aand Layout for Large-Scale Configurable Systems,” IEEE, 1997, pp. 441-446.
Michael J. Wirthlin and Brad L. Hutchings—“Improving Functional Density Using Run-Time Circuit Reconfiguration,” Jun. 1998, p. 247-256.
Electronik, De, Franzis Verlag GmbH—“MIT Programmierbarer Logik Verheirated,” Mar. 31, 1998, vol. 47, No. 7, p. 38.
Bernardo Kastrup et al., “ConCISe: A Complier-Driven CPLD-Based Instruction Set Accelerator,” IEEE, 1999, pp. 92-101.
“List of FPGA-based Computing Machines,” Steve Guccione, <http://www.io.com/.about.guccione//HW.sub.--list.html>, Last updated Mar. 31, 1999.
Timothy J. Callahan et al., “The Garp Architecture and C Complier,” IEEE, Apr. 2000 pp. 62-69.
IBM, “Programmable Manual Cable Assembly Board,” IBM Technical Disclosure Bulletin, vol. 31, No. 12, May 1989, pp. 306-309.
Nanya, “Asynchronous VLSI System Design,” ASP-DAC '98 Tutorials, Feb. 10, 1998, Yokohama, Japan.
Nanya et al. “Scalable-Delay-Insensitive Design: a high-performance approach to dependable asynchronous systems,” Proceedings of International Symposium on Future of Intellectual Integrated Electronics, Mar. 1999, pp. 1-10.
Tsukasa Yamauchi et al., “SOP: A Reconfigurable Massively Parallel System and Its Control-Data-Flow based Compiling Method,” NEC Laboratory, pp. 148-156, IEEE 1996.
Luc Séméria et al., “SpC; Synthesis of Pointers in C Application of Pointer Analysis to the Behavioral Synthesis from C,” 1998, pp. 340-346.
João M.P. Cardoso et al., “Marco-Based Hardware Compilation of Java™ Bytecodes into a Dynamic Reconfigurable Computing System,” IEEE, 1999, pp. 2-11.
Smith Stephen J.
Southgate Timothy J.
Altera Corporation
Ropes & Gray LLP
Suryawanshi Suresh K
LandOfFree
Method for managing resources in a reconfigurable computer... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for managing resources in a reconfigurable computer..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for managing resources in a reconfigurable computer... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2735459