Semiconductor wafer including cracking stopper structure and...

Details Semiconductor wafer including cracking stopper structure and... Semiconductor wafer including cracking stopper structure and...

2011-07-12

2011-07-12

Fahmy, Wael M (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S462000, C438S643000, C438S637000, C438S627000, C438S618000, C438S629000, C438S465000, C438S460000, C438S584000, C438S508000, C438S619000, C257S620000, C257SE23194, C257SE21575, C257SE23170, C257SE23169, C257S773000, C257S725000, C257S775000, C257S750000, C257S774000, C257S700000, C257S383000, C257S524000

Reexamination Certificate

active

07977232

ABSTRACT:
A semiconductor wafer may include, but is not limited to, the following elements. A semiconductor substrate has a device region and a dicing region. A stack of inter-layer insulators may extend over the device region and the dicing region. Multi-level interconnections may be disposed in the stack of inter-layer insulators. The multi-level interconnections may extend in the device region. An electrode layer may be disposed over the stack of inter-layer insulators. The electrode layer may extend in the device region. The electrode layer may cover the multi-level interconnections. A cracking stopper groove may be disposed in the dicing region. The cracking stopper groove may be positioned outside the device region.

REFERENCES:
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patent: 2005/0026397 (2005-02-01), Daubenspeck et al.
patent: 2005/0093169 (2005-05-01), Kajita
patent: 2005/0269702 (2005-12-01), Otsuka
patent: 2005-260059 (2005-09-01), None
patent: 2006-516824 (2006-07-01), None
patent: 2004/073014 (2004-08-01), None
patent: 2004/073014 (2004-08-01), None

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