Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1998-09-04
2000-12-19
Prenty, Mark V.
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257369, H01L 2976
Patent
active
061630594
ABSTRACT:
In the fabrication of an integrated circuit having both N MOSFETs and P MOSFETs in which the respective N-type species and P-type species have substantially different diffusivities, the source implant of the dopant species having a the higher diffusivity is advantageously delayed until a contact masking process step. By delaying the dopant species having the higher diffusivity, depletion of the dopant by subsequent annealing steps is avoided. P MOSFETs formed using a high diffusivity boron implant species in an integrated circuit including both P MOSFETs and N MOSFET are fabricated with no source implant in the source regions during formation of the gate electrodes and sidewall spaces. Once the gate and spacer structures on the surface of a substrate wafer are complete and a contact masking step is performed for patterning contact vias, typically in preparation for contact metallization, contact vias are cut to the surface of the substrate and the substrate in the source area exposed by the vias is implanted with the source dopant. A method of fabricating an integrated circuit includes forming a lightly-doped drain (LDD) MOSFET structure prior to source/drain doping. The LDD MOSFET structure includes a gate formed on a substrate over a gate oxide layer, spacers formed on sides of the gate, LDD doping of the substrate in a source region and a drain region self-aligned with the gate. The method further includes forming an oxide layer over the substrate and LDD MOSFET structure, cutting a contact via through the oxide layer to the substrate surface in the vicinity of the gate and spacer and abutting the source region of the substrate, and implanting a source implant through the contact via into the source of the LDD MOSFET structure.
REFERENCES:
patent: 4561170 (1985-12-01), Doering et al.
patent: 4599789 (1986-07-01), Gasner
patent: 4621412 (1986-11-01), Kobayashi et al.
patent: 4956311 (1990-09-01), Liou et al.
patent: 4997782 (1991-03-01), Bergonzoni
patent: 5036019 (1991-07-01), Yamane et al.
patent: 5304504 (1994-04-01), Wei et al.
patent: 5373178 (1994-12-01), Motoyoshi et al.
patent: 5457060 (1995-10-01), Chang
patent: 5512506 (1996-04-01), Chang et al.
patent: 5521417 (1996-05-01), Wada
patent: 5547885 (1996-08-01), Ogoh
patent: 5547888 (1996-08-01), Yamazaki
patent: 5578509 (1996-11-01), Fujita
patent: 5602055 (1997-02-01), Nicholls et al.
patent: 5607869 (1997-03-01), Yamazaki
patent: 5624863 (1997-04-01), Helm et al.
patent: 5654215 (1997-08-01), Gardner et al.
patent: 5656518 (1997-08-01), Gardner et al.
patent: 5686324 (1997-11-01), Wang et al.
patent: 5789787 (1998-08-01), Kadosh et al.
patent: 5849622 (1998-12-01), Hause et al.
Silicon Processing for the VLSI Era--vol. 2: Process Integration, by S. Wolf, published by Lattice Press, Sunset Beach, CA, 1990, p. 436.
Gardner Mark I.
Hause Frederick N.
Advanced Micro Devices , Inc.
Koestner Ken J.
Prenty Mark V.
LandOfFree
Integrated circuit including source implant self-aligned to cont does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit including source implant self-aligned to cont, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit including source implant self-aligned to cont will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-273081