Method of fabricating a self aligned contact for a capacitor ove

Details Method of fabricating a self aligned contact for a capacitor ove Method of fabricating a self aligned contact for a capacitor ove

1999-07-12

2000-12-19

Tsai, Jey

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

438253, H01L 218242

Patent

active

061630470

ABSTRACT:
A process for fabricating a capacitor over bitline, DRAM device, using a self-aligned contact opening, through, and between the bitline structures, and featuring the formation of insulator spacers, on the sidewall of the bitline structures, formed after the opening of the self-aligned contact, has been developed. The self-aligned contact opening, located through the bitline structures, allows an increase in DRAM cell density to be achieved. The formation of insulator spacers, on the sidewall of the bitline structures, formed after the opening of the self-aligned contact, in a silicon oxide layer, allows silicon oxide to be used as the spacer material, thus resulting in capacitance decrease when compared to counterparts fabricated using silicon nitride spacers.

REFERENCES:
patent: 5134086 (1992-07-01), Ahn
patent: 5369048 (1994-11-01), Hsue
patent: 5409855 (1995-04-01), Jun
patent: 5763306 (1998-06-01), Tsai
patent: 5874335 (1999-02-01), Jenq et al.
patent: 5933726 (1999-02-01), Nishimura et al.

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