Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2011-03-22

2011-03-22

Maldonado, Julio J (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE21646, C257SE27084

Reexamination Certificate

active

07911000

ABSTRACT:
A memory includes a U-shape layer on a substrate; a first diffusion layer provided at an upper part of the U-shaped layer; a second diffusion layer provided at a lower part of the U-shaped layer; a body formed at an intermediate portion of the U-shaped layer between the first and the second diffusion layers; a first gate dielectric film provided on an outer side surface of the U-shaped layer; a first gate electrode provided on the first gate dielectric film; a second gate dielectric film provided on an inner side surface of the U-shaped layer; a second gate electrode provided on the second gate dielectric film; a bit line contact connecting the bit line to the first diffusion layer; a source line contact connecting the source line to the second diffusion layer, wherein cells adjacent in the first direction alternately share the bit line contact and the source line contact.

REFERENCES:
patent: 6239465 (2001-05-01), Nakagawa
patent: 2008/0277725 (2008-11-01), Shino
patent: 8-64778 (1996-03-01), None
patent: 2002-329795 (2002-11-01), None
patent: 2003-86712 (2003-03-01), None
patent: 2005-26366 (2005-01-01), None
patent: 2007-18588 (2007-01-01), None
patent: WO 2009/005075 (2009-01-01), None
U.S. Appl. No. 12/598,866, filed Nov. 4, 2009, Shino.

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