Method and system for testing bit failures in array elements...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Testing or evaluating

Reexamination Certificate

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C716S103000, C716S106000, C716S112000

Reexamination Certificate

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08010934

ABSTRACT:
The invention relates to a method and system for testing bit failures in array elements of an electronic circuit. Said method comprising the steps of changing an original hardware representation (DD) of the array such that errors can be injected in a memory by manipulation of associated read and/or write logic of the memory via input signals, building an emulator model (SME) from said changed hardware representation for emulating the array, and injecting errors into the changed hardware representation for determining the array to get stick capabilities.

REFERENCES:
patent: 6539503 (2003-03-01), Walker
patent: 6829572 (2004-12-01), Crouse, II et al.
patent: 2003/0226062 (2003-12-01), Gender et al.
U.S. Appl. No. 10/035,474, filed Oct. 25, 2001, Barlh et al.

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