SRAM with read and write assist

Details SRAM with read and write assist SRAM with read and write assist

2011-08-23

2011-08-23

Tran, Michael T (Department: 2827)

Static information storage and retrieval

Read/write circuit

C365S191000

Reexamination Certificate

active

08004907

ABSTRACT:
A memory includes an SRAM bitcell including a pair of cross-coupled inverters, wherein a first inverter of the pair includes a first device having a body and a second inverter of the pair includes a second device having a body. A first selection circuit has a first input coupled to a first supply voltage terminal, a second input coupled to a second supply voltage terminal, and an output coupled to a first current electrode of the first device and to a first current electrode of the second device. A second selection circuit has a first input coupled to the first supply voltage terminal, a second input coupled to the second supply voltage terminal, and an output coupled to the body of each of the first and second devices. A word line coupled to the SRAM bitcell is driven by a word line driver coupled to the first supply voltage terminal.

REFERENCES:
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patent: 6977859 (2005-12-01), Takahashi
patent: 7079426 (2006-07-01), Zhang et al.
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patent: 2001/0010642 (2001-08-01), Naffziger et al.
patent: 2003/0179642 (2003-09-01), Winograd et al.
patent: 2004/0032758 (2004-02-01), Cheng et al.
patent: 2008/0198678 (2008-08-01), McClure et al.
patent: 2009/0109723 (2009-04-01), Buer et al.

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