Prefetching in a virtual memory system based upon repeated...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C711S204000, C711S205000, C711S206000, C711S207000, C711SE12022

Reexamination Certificate

active

07958315

ABSTRACT:
A system and method of improved handling of large pages in a virtual memory system. A data memory management unit (DMMU) detects sequential access of a first sub-page and a second sub-page out of a set of sub-pages that comprise a same large page. Then, the DMMU receives a request for the first sub-page and in response to such a request, the DMMU instructs a pre-fetch engine to pre-fetch at least the second sub-page if the number of detected sequential accesses equals or exceeds a predetermined value.

REFERENCES:
patent: 4638426 (1987-01-01), Chang et al.
patent: 4876646 (1989-10-01), Gotou et al.
patent: 5751990 (1998-05-01), Krolak et al.
patent: 5918245 (1999-06-01), Yung
patent: RE37305 (2001-07-01), Chang et al.
patent: 6304962 (2001-10-01), Nair
patent: 6418522 (2002-07-01), Gaertner et al.
patent: 6678795 (2004-01-01), Moreno et al.
patent: 6789171 (2004-09-01), Desai et al.
patent: 6886085 (2005-04-01), Shuf et al.
patent: 6961837 (2005-11-01), Haren et al.
patent: 2004/0123044 (2004-06-01), Franaszek
patent: 2004/0205299 (2004-10-01), Bearden
patent: 2006/0026365 (2006-02-01), Yamazaki
patent: 2006/0206686 (2006-09-01), Banerjee et al.
patent: 2008/0133873 (2008-06-01), Anand et al.
Madhusudhan Talluri and Mark D. Hill. “Surpassing the TLB Performance of Superpages with Less Operating System Support.” 1994. ACM. ASPLOS 1994.
Gokul B. Kandiraju. “Towards Self-Optimizing Memory Management.” May 2004. Pennsylvania State University, Department of Computer Science and Engineering. Ch. 2.
Doug Joseph and Dirk Grunwald. “Prefetching using Markov Predictors.” 1997. ACM. ISCA 1997.
Gokul B. Kandiraju and Anand Sivasubramaniam. “Going the Distance for TLB Prefetching: An Application-driven Study.” 2002. ACM. ISCA 2002.
Inshik Song and Yookun Cho. “Page Prefetching Based on Fault History.” 1993. USENIX. USENIX MACH III Symposium. pp. 203-214.
Jung-Hoon Lee, Jang-Soo Lee, Seh-Woong Jeong, and Shin-Dug Kim. “A Banked-Promotion TLB for High Performance and Low Power.” Sep. 2001. IEEE. ICCD 2001.
Kavita Bala et al., Software Prefetching and Caching for Translation Lookaside Buffers, Proceedings of the First Symposium on Operating System Design and Implementation, Nov. 1994.
Intel Architecture Optimization Reference Manual, 1998, 1999.
Ashley Saulsbury et al., Recency-Based TLB Preloading, ACM, 2000.
Lixin Zhang et al., The Impulse Memory Controller, Sep. 24, 2001.
Notice of Allowability dated Sep. 10, 2010; U.S. Appl. No. 12/015,669.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Prefetching in a virtual memory system based upon repeated... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Prefetching in a virtual memory system based upon repeated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Prefetching in a virtual memory system based upon repeated... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2719095

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.