Semiconductor device and its manufacturing method

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package

Reexamination Certificate

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C257S781000, C257SE23114

Reexamination Certificate

active

07919843

ABSTRACT:
There is provided a semiconductor device10including a solder resist16for protecting a wiring pattern14electrically connected to a semiconductor chip11via an internal connection terminal12, characterized in that the solder resist16is arranged to cover the upper surface of the portion of the wiring pattern14not corresponding to the arrangement region of the external connection terminal17and the side surface14B of the wiring pattern14and that the area of the solder resist16assumed when the upper surface13A of an insulation layer13is viewed from above is substantially the same as that of the wiring pattern14assumed when the upper surface13A of the insulation layer13is viewed from above.

REFERENCES:
patent: 6355500 (2002-03-01), Miyazaki et al.
patent: 2008-084958 (2008-04-01), None

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