Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2011-06-14
2011-06-14
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S764000
Reexamination Certificate
active
07962809
ABSTRACT:
A memory circuit includes a memory interface including an address line and a data line. A first memory is configured to i) receive addresses transmitted on the address line of the memory interface and ii) output data in response to the addresses. Content addressable memory (CAM) is configured to i) monitor the addresses transmitted on the address line of the memory interface and ii) output error correction coding (ECC) bits in response to the addresses. An ECC circuit is configured to receive the ECC bits and the data. The memory interface is configured to selectively receive, via the data line of the memory interface, one of the data from the first memory and an output of the ECC circuit.
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Azimi Saeed
Sutardja Sehat
Britt Cynthia
Marvell International Ltd.
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