Decoder circuit

Details Decoder circuit Decoder circuit

2011-06-28

2011-06-28

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

C326S106000, C326S108000

Reexamination Certificate

active

07969200

ABSTRACT:
A normally operable decoder circuit is obtained without entailing a delay in decoding operation, an increase in circuit area, and an increase in circuit design cost. An NMOS transistor in a high-voltage circuit portion is inserted between the output of a NAND gate and a node, and receives an input signal at the gate electrode thereof. A load current generating portion in the high-voltage circuit portion includes PMOS transistors coupled in series between a high power supply voltage and the node. One of the PMOS transistor receives a control signal at the gate electrode thereof. The other PMOS transistor receives a control signal at the gate electrode thereof. An inverter receives a signal obtained from the node as an input signal, and outputs the inverted signal thereof as an output signal.

REFERENCES:
patent: 4893275 (1990-01-01), Tanaka et al.
patent: 5781497 (1998-07-01), Patel et al.
patent: 5808482 (1998-09-01), Rountree
patent: 2001-101881 (2001-04-01), None

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