Stack package and method for manufacturing the same

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C257S620000, C257S686000, C257SE23085

Reexamination Certificate

active

07871925

ABSTRACT:
A stack package comprises a substrate having a circuit pattern; at least two semiconductor chips stacked on the substrate, having a plurality of through-via interconnection plugs and a plurality of guard rings which surround the respective through-via interconnection plugs, and connected with each other by the medium of the through-via interconnection plugs; a molding material for molding an upper surface of the substrate including the stacked semiconductor chips; and solder balls mounted to a lower surface of the substrate.

REFERENCES:
patent: 6122704 (2000-09-01), Hass et al.
patent: 7161231 (2007-01-01), Koike
patent: 7189637 (2007-03-01), Uchikoshi et al.
patent: 7303986 (2007-12-01), Uchikoshi et al.
patent: 2006/0220230 (2006-10-01), Tanaka et al.
patent: 2007/0045780 (2007-03-01), Akram et al.
patent: 1338117 (2002-02-01), None
patent: 2001-68618 (2001-03-01), None
patent: 1020030050665 (2003-06-01), None
patent: 1020060049323 (2006-05-01), None
patent: 1020060073463 (2006-06-01), None
patent: 01/39267 (2001-05-01), None

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