Method and related apparatus for reducing CHIPSET power...

Details Method and related apparatus for reducing CHIPSET power... Method and related apparatus for reducing CHIPSET power...

2011-08-30

2011-08-30

Lee, Thomas (Department: 2116)

Electrical computers and digital processing systems: support

Digital data processing system initialization or configuration

C713S100000, C713S300000, C713S310000, C713S320000, C713S323000, C713S324000, C713S340000, C711S001000, C711S002000, C711S005000, C710S008000, C710S009000

Reexamination Certificate

active

08010775

ABSTRACT:
A method for reducing computer system power consumption. The computer system includes a memory module having a plurality of address pins, and a chipset having a plurality of driving units for driving the address pins. The method includes obtaining number of required address pins by detecting a capacity of the memory module, and disabling the driving units so as to make a number of the active driving units substantially equal to the number of the required address pins.

REFERENCES:
patent: 5875201 (1999-02-01), Bauman et al.
patent: 6038637 (2000-03-01), Berube et al.
patent: 6199153 (2001-03-01), Razdan et al.
patent: 2006/0004981 (2006-01-01), Bains
patent: 2006/0039205 (2006-02-01), Cornelius
patent: 2006/0041713 (2006-02-01), Charles et al.
patent: 7-84988 (1995-03-01), None

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