Hybrid orientation CMOS with partial insulation process

Details Hybrid orientation CMOS with partial insulation process Hybrid orientation CMOS with partial insulation process

2011-03-29

2011-03-29

Trinh, Michael (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S152000, C438S478000, C438S481000, C257SE21413

Reexamination Certificate

active

07915100

ABSTRACT:
The present invention provides a method of integrated semiconductor devices such that different types of devices are formed upon a specific crystallographic orientation of a hybrid substrate. In accordance with the present invention, junction capacitance of one of the devices is improved in the present invention by forming the source/drain diffusion regions of the device in an epitiaxial semiconductor material such that they are situated on a buried insulating layer that extends partially underneath the body of the second semiconductor device. The second semiconductor device, together with the first semiconductor device, is both located atop the buried insulating layer. Unlike the first semiconductor device in which the body thereof is floating, the second semiconductor device is not floating. Rather, it is in contact with an underlying first semiconducting layer.

REFERENCES:
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patent: 4933298 (1990-06-01), Hasegawa
patent: 5384473 (1995-01-01), Yoshikawa et al.
patent: 5731217 (1998-03-01), Kadosh et al.
patent: 6998684 (2006-02-01), Anderson et al.
patent: 2004/0121507 (2004-06-01), Bude et al.

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