Method of fabricating a semiconductor integrated circuit device

Details Method of fabricating a semiconductor integrated circuit device Method of fabricating a semiconductor integrated circuit device

1998-12-14

2000-12-19

Wilczewski, Mary

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438624, 438788, H01L 21443

Patent

active

061627232

ABSTRACT:
A semiconductor integrated circuit device selectively decreasing the parasitic capacitance between wiring lines of a wiring layer is provided. This device is comprised of a semiconductor substructure with a main surface, an insulating layer formed on the main surface of the substructure, a first patterned conductive layer formed on the insulating layer to serve as a first-level wiring layer, and an interlevel dielectric layer formed on the insulating layer to cover the first-level wiring layer. The first-level wiring layer includes a first plurality of wiring lines and a second plurality of wiring lines. The first plurality of wiring lines are located apart from each other at gaps equal to or smaller than a specific value. The second plurality of wiring lines are located apart from each other at gaps larger than the specific value. The interlevel dielectric layer includes voids selectively located in the gaps of the first plurality of wiring lines, thereby decreasing a parasitic capacitance between the first plurality of wiring lines. The tops of the voids are lower than the tops of the first-level wiring layer, respectively.

REFERENCES:
patent: 5545919 (1996-08-01), Ueda et al.
patent: 5698901 (1997-12-01), Endo
patent: 5773361 (1998-06-01), Cronin et al.
patent: 5837618 (1998-11-01), Avanzino et al.
patent: 5856703 (1999-01-01), Manning
patent: 5955786 (1999-09-01), Avanzino et al.
patent: 5981397 (1999-11-01), Manning

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