Semiconductor memory device and manufacturing method thereof

Details Semiconductor memory device and manufacturing method thereof Semiconductor memory device and manufacturing method thereof

2011-03-08

2011-03-08

Louie, Wai-Sing (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S317000, C257S330000, C257SE27089

Reexamination Certificate

active

07902584

ABSTRACT:
This disclosure concerns a semiconductor memory device including a substrate; an insulating film provided above the substrate; a semiconductor layer provided above the insulating film and extending in a plane which is parallel to a surface of the substrate; a first gate dielectric film provided on an inner wall of a opening penetrating through the semiconductor layer; a first gate electrode penetrating through the opening and isolated from the semiconductor layer by the first gate dielectric film; a second gate dielectric film formed on a side surface and an upper surface of the semiconductor layer located on the first gate electrode; and a second gate electrode provided on the side surface and the upper surface of the semiconductor layer via the second gate dielectric film, isolated from the first gate electrode, and superimposed on the first gate electrode.

REFERENCES:
patent: 4996574 (1991-02-01), Shirasaki
patent: 2007/0034925 (2007-02-01), Lee et al.
patent: 2008/0149984 (2008-06-01), Chang et al.
patent: 2008/0150075 (2008-06-01), Chang
patent: 2006-100600 (2006-04-01), None
Takashi Ohsawa, et al., “Memory Design Using a One-Transistor Gain Cell on SOI”, IEEE Journal of Solid-State Circuits, vol. 37, No. 11, Nov. 2002, pp. 1510-1522.

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