Sub-lithographic dimensioned air gap formation and related...

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having air-gap dielectric

Reexamination Certificate

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C438S400000, C438S411000, C257S506000, C257S522000

Reexamination Certificate

active

07943480

ABSTRACT:
Sub-lithographic dimensioned air gap formation and related structure are disclosed. In one embodiment, a method includes forming a dielectric layer including interconnects on a substrate; depositing a cap layer on the dielectric layer; depositing a photoresist over the cap layer; patterning the photoresist to include a first trench pattern at most partially overlying the interconnects; forming a spacer within the first trench pattern to form a second trench pattern having a sub-lithographic dimension; transferring the second trench pattern into the cap layer and into the dielectric layer between the interconnects; and depositing another dielectric layer to form an air gap by pinching off the trench in the dielectric layer.

REFERENCES:
patent: 6475904 (2002-11-01), Okoroanyanwu et al.
patent: 2004/0127016 (2004-07-01), Hoog et al.
“Method to Generate Airgaps With A Template First Scheme and a Self Aligned Blockout Mask”, Colburn et al., U.S. Appl. No. 11/518,773, filed Sep. 11, 2006.
Nitta, Satya, “A Multilevel Copper/Low-k//Airgap BEOL Technology”, Advanced Metalization Conference 2007, IBM Corporation, 20 pages.

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