Method for fabricating semiconductor device

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C438S627000, C438S653000, C438S668000, C438S672000, C438S675000, C257SE21575, C257SE21577, C257SE21584, C257SE21597

Reexamination Certificate

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07998862

ABSTRACT:
A method of fabricating a semiconductor device includes forming a via hole in a semiconductor substrate, forming an isolation layer on an inner side of the via hole, forming a diffusion barrier layer over an upper portion of the semiconductor substrate and the inner side of the via hole where the isolation layer is formed, arranging a solvent, which contains electrically charged metal particles, on the semiconductor substrate where the diffusion barrier layer is formed, and filling the via hole with the metal particles by moving the metal particles using applied external force. The applied external force said includes a voltage causing an electric current to flow between the semiconductor substrate and the solvent, an electrical field applied between the semiconductor substrate and the solvent, or a magnetic field applied between the semiconductor substrate and the solvent.

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patent: 3084021 (2000-09-01), None
patent: 2003-218200 (2003-07-01), None
Okuno, Atsushi et al., “Filling the via hold of IC by VPES (Vacuum Printing Encapsulation Systems) for stacked chip (3D packaging)”, 2002 Electronic Components and Technology Conference, 2002, pp. 1444-1448, IEEE.
Keigler, Arthur et al., “Optimized TSV Filling Processes Reduce Costs”, Semiconductor International, May 2009, pp. 19-22, vol. 32.

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