MOS type semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257SE29197

Reexamination Certificate

active

08004037

ABSTRACT:
A surface between gate electrodes in an MOS gate structure is patterned so that missing portions are partially provided in surfaces of n+emitter regions to thereby enlarge surface areas of p+contact regions surrounded by the surfaces of the n+emitter regions. In this manner, a highly reliable MOS type semiconductor device is provided which is improved in breakdown tolerance by suppressing an increase in the gain of a parasitic transistor caused by photo pattern defects produced easily in accordance with minute patterning in a process design rule.

REFERENCES:
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patent: 5448083 (1995-09-01), Kitagawa et al.
patent: 5585651 (1996-12-01), Kitagawa et al.
patent: 5689121 (1997-11-01), Kitagawa et al.
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patent: 6262470 (2001-07-01), Lee et al.
patent: 7056779 (2006-06-01), Hattori
patent: 2006/0081919 (2006-04-01), Inoue et al.
patent: 0 538 004 (1993-04-01), None
patent: 5-110085 (1993-04-01), None
patent: 7-135309 (1995-05-01), None
H.Yilmaz; “Cell Geometry Effect on IGT Latch-UP”, IEEE Electron Device Letters, vol. EDL-6, No. 8, Aug. 1985, pp. 419-421.

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