Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2011-08-23
2011-08-23
Sandvik, Benjamin P (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257SE29197
Reexamination Certificate
active
08004037
ABSTRACT:
A surface between gate electrodes in an MOS gate structure is patterned so that missing portions are partially provided in surfaces of n+emitter regions to thereby enlarge surface areas of p+contact regions surrounded by the surfaces of the n+emitter regions. In this manner, a highly reliable MOS type semiconductor device is provided which is improved in breakdown tolerance by suppressing an increase in the gain of a parasitic transistor caused by photo pattern defects produced easily in accordance with minute patterning in a process design rule.
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H.Yilmaz; “Cell Geometry Effect on IGT Latch-UP”, IEEE Electron Device Letters, vol. EDL-6, No. 8, Aug. 1985, pp. 419-421.
Fuji Electric & Co., Ltd.
Kuo W. Wendy
Rossi Kimms & McDowell LLP
Sandvik Benjamin P
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