Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2011-01-04
2011-01-04
Bragdon, Reginald G (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S113000, C711SE12021
Reexamination Certificate
active
07865667
ABSTRACT:
In one embodiment, a processor is provided. The processor includes at least two cores, where each of the cores include a first level cache memory. Each of the cores are multi-threaded. In another embodiment, each of the cores includes four threads. In another embodiment a crossbar is included. A plurality of cache bank memories in communication with the at cores through the crossbar is provided. Each of the plurality of cache bank memories are in communication with a main memory interface. In another embodiment a buffer switch core in communication with each of the plurality of cache bank memories is also included. A server and a method for optimizing the utilization of a multithreaded processor core are also provided.
REFERENCES:
patent: 6341347 (2002-01-01), Joy et al.
patent: 2002/0087803 (2002-07-01), Jones et al.
Kohn Leslie D.
Olukotun KunIe A.
Wong Michael K.
Bragdon Reginald G
Martine & Penilla & Gencarella LLP
Oracle America Inc.
Wang Victor W
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