ROM testing circuit

Details ROM testing circuit ROM testing circuit

1998-06-12

2000-05-16

Nguyen, Hoa T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

714733, 3241581, 324763, G11C 2900, G01R 3128, G01R 3102

Patent

active

060651423

ABSTRACT:
Disclosed is A ROM testing circuit for testing ROMs embedded in respective chips arranged on a wafer, which ROM testing circuit comprises units which are embedded in the respective chips, wherein each of the units comprises: input means for receiving a signal outputted from the ROM embedded in one adjacent chip or from each of the ROMs embedded in two or more respective adjacent chips; output means for outputting a signal outputted from the ROM formed in the chip to which the unit belongs to the one adjacent chip or to the two or more adjacent chips; and means for comparing the signal outputted from the ROM in the chip to which the unit belongs with the signal or signals inputted via the input means. With this arrangement, all adjacent chips can be tested with respect to their ROMs simultaneously.

REFERENCES:
patent: 5017848 (1991-05-01), Takahashi
patent: 5055774 (1991-10-01), Catt
patent: 5440724 (1995-08-01), Boothroyd et al.
patent: 5442643 (1995-08-01), Adachi
patent: 5446395 (1995-08-01), Goto

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