Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reissue Patent
2011-03-15
2011-03-15
Baker, Stephen M (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
C714S807000
Reissue Patent
active
RE042228
ABSTRACT:
Cyclic-redundancy-code (“CRC”) information that is received along with a frame from a fiber-channel is stored in an on-chip frame buffer, and later checked to ensure the integrity of the data while in the frame buffer. In various embodiments, data frames, along with their CRC information, are stored into a data-frame buffer, and/or non-data frames along with their CRC information are stored into a receive-non-data-frame buffer. The improved communications channel system includes a channel node having dual ports, each port supporting a fiber-channel arbitrated-loop serial communications channel. The serial communications channels each include CRC on data transmissions on the channel, an on-chip frame memory located on-chip in the channel node that receives a data frame and the frame's associated CRC from the communications channel, and an integrity apparatus that later uses the received associated CRC for data-integrity checking of data in the on-chip frame memory. In addition, a method for using CRC for data integrity in on-chip memory is described.
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Miller Michael H.
Westby Judy Lynn
Baker Stephen M
Magee Theodore M.
Seagate Technology LLC
Westman Champlin & Kelly P.A.
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