Spacer double patterning for lithography operations

Details Spacer double patterning for lithography operations Spacer double patterning for lithography operations

2011-04-19

2011-04-19

Richards, N Drew (Department: 2895)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

C438S238000, C438S241000, C438S253000, C438S257000, C438S381000, C257SE21034

Reexamination Certificate

active

07927928

ABSTRACT:
Systems and methods of semiconductor device fabrication and layout generation are disclosed. An exemplary method includes processes of depositing a layer of a first material and patterning the layer to form an initial pattern, wherein the initial pattern defines critical features of the layout elements using a single exposure; depositing spacer material over the first pattern on the substrate and etching the spacer material such that the spacer material is removed from horizontal surfaces of the substrate and the first pattern but remains adjacent to vertical surfaces of the first pattern; removing the initial pattern from the substrate while leaving the spacer material in a spacer pattern; filling the spacer pattern with final material; and trimming the filled pattern to remove portions of the final material beyond dimensions of the layout elements.

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Huckabay, J., Staud, W., Naber, R., Oosten, A., Nikolski, P., Hsu, S., Socha, R., Dusa, M., Flagello, D., “Process results using automatic pitch decomposition and double patterning technology (DPT) at k1eff<0.20.” SPIE, vol. 6349, 2006.

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