Concurrent input/output control and integrated error...

Details Concurrent input/output control and integrated error... Concurrent input/output control and integrated error...

2011-05-31

2011-05-31

Tsai, Henry W (Department: 2184)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S015000, C710S016000, C710S017000, C710S018000, C710S019000, C710S021000, C710S057000, C714S048000, C714S100000, C714S769000, C370S216000, C370S242000

Reexamination Certificate

active

07953907

ABSTRACT:
A FIFO memory has integrated error management to react to different errors according to the current state of operation of the input and output as well as internal conditions such as buffer memory status. The FIFO memory completes or aborts current operations according to state and leaves the FIFO memory in known condition following error handling. Thus, data sent to a host avoids data gaps or data overlaps because the FIFO memory leaves operations in a known state before reporting the error to a controller.

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