Latency measurements for wireless communications

Details Latency measurements for wireless communications Latency measurements for wireless communications

2011-04-12

2011-04-12

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S093000

Reexamination Certificate

active

07924054

ABSTRACT:
A programmable logic device (PLD), is provided that includes: a plurality of SERDES channels; a programmable logic fabric configured to implement an interface for a standardized cellular base station system; wherein the interface receives data words from the SERDES channels and transmits data words to the SERDES channels, and wherein a standard corresponding to the standardized base station system restricts a latency with regard to flow of the data words through the interface, the data words being arranged into frames; and a timing measurement circuit configured to measure a delay between a detection of a first timing point in the frames at first location in the PLD with respect to the interface and a detection of a second timing point in the frames at a second location in the PLD with respect to the interface.

REFERENCES:
patent: 7519879 (2009-04-01), Woodward et al.
CPRI Specification V4.0, Common Public Radio Interface (CPRI; Interface Specification, Jun. 3, 2008; 96 pages.

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