Synchronous page-mode phase-change memory with ECC and RAM...

Details Synchronous page-mode phase-change memory with ECC and RAM... Synchronous page-mode phase-change memory with ECC and RAM...

2011-06-21

2011-06-21

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Systems using particular element

Amorphous

C365S238500, C365S200000

Reexamination Certificate

active

07965546

ABSTRACT:
Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data and is relatively long. A page-mode caching PCM device has a lookup table (LUT) that caches write data that is later written to an array of PCM banks. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the relatively slow PCM. Host read data can be supplied by the LUT or fetched from the PCM banks. A multi-line page buffer between the PCM banks and LUT allows for larger block transfers using the LUT. Error-correction code (ECC) checking and generation is performed for data in the LUT, hiding ECC delays for data writes into the PCM banks.

REFERENCES:
patent: 7471556 (2008-12-01), Chow et al.
patent: 7606111 (2009-10-01), Lee et al.

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