Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2011-05-24
2011-05-24
Garber, Charles (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S182000, C257S241000, C257S266000, C257SE21411, C257SE23145, C257SE33012, C257SE51040, C977S708000, C977S720000, C977S723000, C977S742000, C977S743000, C977S750000, C977S751000, C977S779000, C977S784000, C977S789000, C977S796000
Reexamination Certificate
active
07947542
ABSTRACT:
A method for making a thin film transistor, the method comprising the steps of: (a) providing a carbon nanotube array and an insulating substrate; (b) pulling out a carbon nanotube film from the carbon nanotube array by using a tool; (c) placing at least one carbon nanotube film on a surface of the insulating substrate, to form a carbon nanotube layer thereon; (d) forming a source electrode and a drain electrode; wherein the source electrode and the drain electrode being spaced therebetween, and electrically connected to the carbon nanotube layer; and (e) covering the carbon nanotube layer with an insulating layer, and a gate electrode being located on the insulating layer.
REFERENCES:
patent: 6423583 (2002-07-01), Avouris et al.
patent: 6814832 (2004-11-01), Utsunomiya
patent: 6921575 (2005-07-01), Horiuchi et al.
patent: 7285501 (2007-10-01), Mardilovich et al.
patent: 7399400 (2008-07-01), Soundarrajan et al.
patent: 7537975 (2009-05-01), Moon et al.
patent: 2002/0163079 (2002-11-01), Awano
patent: 2004/0251504 (2004-12-01), Noda et al.
patent: 2005/0061496 (2005-03-01), Matabayas
patent: 2005/0079659 (2005-04-01), Duan et al.
patent: 2005/0106846 (2005-05-01), Dubin
patent: 2005/0189535 (2005-09-01), Hsueh et al.
patent: 2006/0249817 (2006-11-01), Kawase et al.
patent: 2007/0004191 (2007-01-01), Gu et al.
patent: 2007/0012922 (2007-01-01), Harada et al.
patent: 2007/0029612 (2007-02-01), Sandhu
patent: 2007/0069212 (2007-03-01), Saitoh et al.
patent: 2007/0085460 (2007-04-01), Harutyunyan et al.
patent: 2007/0108480 (2007-05-01), Nanai et al.
patent: 2007/0132953 (2007-06-01), Silverstein
patent: 2007/0138010 (2007-06-01), Ajayan
patent: 2007/0273796 (2007-11-01), Silverstein et al.
patent: 2007/0273797 (2007-11-01), Silverstein et al.
patent: 2007/0273798 (2007-11-01), Silverstein et al.
patent: 2008/0042287 (2008-02-01), Furukawa et al.
patent: 2008/0134961 (2008-06-01), Bao et al.
patent: 2008/0173864 (2008-07-01), Fujita et al.
patent: 2008/0252202 (2008-10-01), Li et al.
patent: 2008/0265293 (2008-10-01), Lee et al.
patent: 2008/0273280 (2008-11-01), Chen et al.
patent: 2008/0277718 (2008-11-01), Ionescu et al.
patent: 2009/0098453 (2009-04-01), Liu et al.
patent: 2009/0159891 (2009-06-01), Daniel et al.
patent: 2009/0224292 (2009-09-01), Asano et al.
patent: 2009/0256594 (2009-10-01), Zhu
patent: 2009/0272967 (2009-11-01), Afzali-Ardakani et al.
patent: 2009/0282802 (2009-11-01), Cooper et al.
patent: 2010/0028613 (2010-02-01), Schmidt et al.
patent: 2010/0252802 (2010-10-01), Numata et al.
patent: 1484865 (2004-03-01), None
patent: 1490856 (2004-04-01), None
patent: 1745468 (2006-03-01), None
patent: 1823426 (2006-08-01), None
patent: 1853268 (2006-10-01), None
patent: 2007-73706 (2007-03-01), None
patent: 2007-123870 (2007-05-01), None
patent: 2009-32894 (2009-02-01), None
patent: WO2004032193 (2004-04-01), None
patent: WO2006093601 (2006-09-01), None
patent: WO2007089322 (2007-08-01), None
patent: WO2007126412 (2007-11-01), None
patent: WO2008075642 (2008-06-01), None
Jiang et al. (“Spinning and processing continuous yarns from 4-inch wafer scale super-aligned carbon nanotube arrays”, Advanced Materials, 18, pp. 1505-1510, 2006).
IBM research article on IBM research site (enclosed herein, 2004).
Minko et al. (“Two-level structured self-adaptive surfaces with reversibly tunable properties”, Journal of American Chemical Society, 125, pp. 3896-3900, 2003), (hereinafter, Minko).
Cao et al. (“Flow-induced planar assembly of parallel carbon nanotubes and crossed nanotube junctions”, J. of Nanoscience and Nanotechonolgy, vol. 5, pp. 1177-1180, 2005).
R. E. I. Schropp, B. Stannowski, J. K. Rath, New challenges in thin film transistor research, Journal of Non-Crystalline Solids, 299-302, 2002, 1304-1310, 2002.
Hines “Nanotransfer printing of organic and carbon nanotube thin-film transistors on plastic substrates”, Applied Physics Letters, 86,163101 (2005).
Li “Removal of shells of multi-wall carbon nanotubes by repeatedly scanning bias voltage” Science in China Ser. E, Technological Sciences, vol. 47 No. 1 pp. 1-5 (2004).
Ryu “Low-Temperature Growth of Carbon Nanotube by Plasma-Enhanced Chemical Vapor Deposition using Nickel Catalyst”. Jpn. J. Appl. Phys. vol. 42, pp. 3578-3581 (2003).
Meitl et al., Solution Casting and Transfer Printing Single-Walled Carbon Nanotube Films, Nano Letters, 2004, vol. 4, No. 9.
Fan Shou-Shan
Jiang Kai-Li
Liu Kai
Abdelaziez Yasser A
Bonderer D. Austin
Garber Charles
Hon Hai Precision Industry Co. Ltd.
Tsinghua University
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