Dynamic random access memory device suppressing need for...

Details Dynamic random access memory device suppressing need for... Dynamic random access memory device suppressing need for...

2011-01-04

2011-01-04

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S102000, C365S149000, C365S210100, C365S196000, C365S202000, C365S204000, C365S205000, C365S207000, C365S210120

Reexamination Certificate

active

07864598

ABSTRACT:
In one embodiment, a semiconductor memory device includes a plurality of pairs of bit lines, each of said pairs including a first bit line, a second bit line, a memory cell coupled to said first bit line, a sense amplifier determining the logical value stored in the memory cell according to a potential difference between the first and the second bit line, a reference voltage generation circuit, and a reference voltage supply switch coupling an output of the reference voltage generation circuit to the second bit line.

REFERENCES:
patent: 6914840 (2005-07-01), Agata
patent: 7391639 (2008-06-01), Gogl
patent: 2009/0027984 (2009-01-01), Mizuno et al.
patent: 2004-265533 (2004-09-01), None

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