Process variation tolerant memory design

Details Process variation tolerant memory design Process variation tolerant memory design

2011-07-12

2011-07-12

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Optimization

C716S113000, C716S100000

Reexamination Certificate

active

07979832

ABSTRACT:
Methods and systems for designing process variation tolerant memory are disclosed. A memory circuit is divided into functional blocks. A statistical distribution is calculated for each of the functional blocks. Then, the distributions of each block are combined to verify a credibility of the circuit. The credibility is verified if the circuit meets a predetermined yield.

REFERENCES:
patent: 5438527 (1995-08-01), Feldbaumer
patent: 6584036 (2003-06-01), Kurjanowicz et al.
patent: 7505345 (2009-03-01), Wang et al.
patent: 2002/0131320 (2002-09-01), Kurjanowicz et al.
patent: 2004/0122642 (2004-06-01), Scheffer
patent: 2006/0095888 (2006-05-01), Li et al.
patent: 2006/0203581 (2006-09-01), Joshi et al.
patent: 2008/0071511 (2008-03-01), Lin
patent: 2008/0106963 (2008-05-01), Wang et al.
patent: 2009/0310430 (2009-12-01), Chuang et al.
Mukhopadhyay S. et al.; “Modeling of Failure Probability and Statistical Design of SRAM Array for Yield Enhancement in Nanoscaled CMOS”; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems; IEEE USA, vol. 24, No. 12, Dec. 2005; pp. 1859-1880; XP002476433; ISSN: 0278-0070.
Heald, R. et al.; “Variability in sub-100nm SRAM Designs”; Computer Aided Design, 2004; ICCAD-2004; IEEE/ACM International Conference on San Jose, CA, USA; Nov. 7-11, 2004; Piscataway, NJ, USA; IEEE; Nov. 7, 2004, pp. 347-352; XP010763285; ISBN: 0-7803-8702-3.
Bharadwaj, S. Amrutur et al; A Replica Technique for Wordline and Sense Control in Low-Power SRAM'S; IEEE Journal of Solid-State Circuits, IEEE Service Center, Piscataway, NJ, USA; vol. 33, No. 8; Aug. 1998, XP011060780; ISSN: 0018-9200.
Simon, J. Lovett et al.; “Yield and Matching Implications for Static RAM Memory Array Sense-Amplifier Design”; IEEE Journal of Solid-State Circuits, IEEE Service Center, Piscataway, NJ, US; vol. 35, No. 8; Aug. 2000; XP011061307; ISSN: 0018-9200.
International Search Report—PCT/US07/086249, International Search Authority—European Patent Office—May 14, 2008.
Peng, Tao; “How Much Mismatch Should Be Simulated in the High Density SRAM Sense Amplifier Design”, Reliability Physics Symposium, 2005 Proceedings, 43rd Annual. 2005 IEEE International San Jose, CA, USA Apr. 17-21, 2005, Piscataway, NJ, USA, IEEE, (Apr. 17, 2005), pp. 672-673, XP010827010.
Written Opinion—PCT/US07/086249, International Search Authority—European Patent Office—May 14, 2008.
H. Nho et al., Statistical simulation methodology for sub-100nm memory design, Electronic Letters, Aug. 8, 2007, vol. 43, No. 16.

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